1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a silicon/germanium alloy layer deposited onto the surface of the active region of the transistor.
2. Description of the Related Art
The ongoing trend in electronics towards more and more complex integrated circuits requires the dimensions of electronic devices to decrease in order to achieve a higher and higher integration density.
Transistors are the dominant circuit elements in current integrated circuits. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit are as small as possible, so as to enable a high integration density.
Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials such as, for example, dopant atoms or ions may be introduced into the original semiconductor layer.
A metal-oxide-semiconductor field effect transistor (MOSFET) or generally a field effect transistor (FET), irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises a source and a drain region, highly doped with dopants of the same species. An inversely or weakly doped channel region is then arranged between the drain and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, may be controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on, among other things, the mobility of the charge carriers and the distance along the transistor width direction between the source and drain regions, which is also referred to as channel length. For example, by reducing the channel length, the channel resistivity decreases. Thus, an increased switching speed and higher drive current capabilities of a transistor may be achieved by decreasing the transistor channel length.
When fabricating transistors with typical gate dimensions below 50 nm, the so-called “high-k/metal gate” (HKMG) technology has by now become the new manufacturing standard. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices. By high-k material it is referred to a material with a dielectric constant “k” higher than 10. Examples of high-k materials used as insulating layers in gate electrodes are tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2) and the like.
HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges and requires new integration schemes with respect to the conventional poly/SiON technology.
For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level. A thin “work function metal” layer is inserted for this purpose between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage may thus be adjusted by varying the thickness of the metal layer.
Currently, two different schemes exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages such as dopant ion implantation, source and drain region formation and substrate silicidation are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high-temperature source/drain formation and all silicide annealing cycles have been carried out.
In order to further tune the transistor threshold voltage, an epitaxial semiconductor alloy film is introduced in the transistor channel region. The epitaxial semiconductor alloy film is particularly advantageous for reducing the threshold voltage when using the gate-first HKMG approach. In the case of silicon-based devices, this semiconductor alloy film is typically implemented as a silicon/germanium (SiGe) alloy thin film epitaxially grown onto a portion of the substrate surface included in the channel region. An SiGe layer or, in general, a semiconductor alloy layer formed as described above will be hereinafter referred to as a “channel SiGe layer” or “channel semiconductor alloy layer,” respectively.
FIG. 1a shows a cross-sectional view of a semiconductor structure 100 during an early stage of the fabrication process. As shown, the device 100 comprises a substrate 101, such as a semiconductor material and the like, above which a semiconductor layer 102 is formed. The semiconductor layer 102 is typically made of a silicon single crystal. The semiconductor layer 102 is laterally divided into a plurality of active regions 102a, which are to be understood as semiconductor regions in and above which one or more transistors are to be formed. For convenience, a single active region 102a is illustrated. Separation regions not shown in the figures might laterally delimit active regions 102a. Separation regions may, for example, be implemented as shallow trench isolations.
Depending on the overall device requirements, the substrate 101 and the semiconductor layer 102, for instance initially provided as a silicon material, may form an SOI (silicon-on-insulator) architecture when a buried insulating material (not shown) is formed directly below the semiconductor layer 102. In other cases, initially the semiconductor layer 102 represents a part of the crystalline material of the substrate 101 when a bulk configuration is to be used for the device 100.
A semiconductor alloy layer 104, typically an SiGe layer, lies on top of the upper surface of the semiconductor layer 102. In particular, the semiconductor alloy layer 104 is typically formed by means of a deposition process on the upper surface of the silicon layer 102 within the active region 102a. The semiconductor alloy layer 104 exposes its upper surface 104u to the outside. The semiconductor alloy layer 104 is formed onto the semiconductor layer 102 so that a portion thereof will be included in the channel region of a transistor to be formed partly in and partly on the semiconductor layer 102. Thus, the semiconductor alloy 104 is a channel semiconductor alloy layer.
It is here pointed out that, in some approaches, the semiconductor alloy layer 104 is formed after defining the active region 102a and separation regions. On the other hand, in other approaches, an early deposition of the semiconductor alloy layer 104 onto the surface of the semiconductor layer 102 may be preferred, followed by the definition of the active region 102a and, where required, of the separation regions.
As shown in FIG. 1b, a cleaning process 182 typically follows the formation of the channel semiconductor alloy layer 104. The cleaning process 182 is crucial in order to form a good quality gate oxide on the surface of the semiconductor layer 104.
The cleaning process 182 may include a wet etch. The wet etch may include using one or more acids. For example, hydrofluoric acid (HF) may be used. The wet etch may also be performed using a solvent. For example, acetone or methanol may be used. Furthermore, wet etch may include using a solution of a hydroxide in water. Alternatively or additionally, the cleaning process 182 may include a dry etch. For example, an etch based on a plasma may be used.
During cleaning 182, the semiconductor structure 100 exposes the upper surface 104u of the semiconductor alloy layer 104. As it turns out, the upper surface 104u of the semiconductor alloy layer 104 is extremely unstable and is likely damaged or eroded by cleaning 182, particularly when the semiconductor alloy layer 104 is comprised of an SiGe alloy. Usually, the extent to which surface 104u is eroded or etched by cleaning 182 is not uniform across the whole device surface. Rather, the semiconductor alloy layer 104 may likely be eroded by the cleaning process 182 to different extents depending on the position across the layer surface. As a consequence, the semiconductor alloy layer 104 has different thicknesses depending on the layer portion. As will be explained in the following, this feature of the semiconductor alloy layer 104 is undesirable since the threshold voltage of a FET is extremely sensitive to the thickness of the channel semiconductor alloy layer 104. A pronounced thickness fluctuation of the layer 104 may then result in two FETs fabricated in different areas of the same device having different threshold voltages, or even in the threshold voltage of a single FET not being clearly defined as designed.
FIG. 1c shows a cross-section of the semiconductor structure 100 in a fabrication stage subsequent to that shown in FIG. 1b. A transistor 150 has been partly formed in and on top of the active region 102a of the semiconductor layer. In particular, a gate electrode structure 160 has been formed on the semiconductor layer 102. The gate electrode structure 160 has been formed on the channel semiconductor alloy layer 104 and, more specifically, on the upper surface 104u of the channel semiconductor alloy layer 104.
The gate electrode 160 comprises a gate electrode material 162, which may be, for example, polysilicon. The gate electrode 160 may have any appropriate geometric configuration, for instance in terms of length and width. For example, the gate length, i.e., in FIG. 1c, the horizontal extension of the gate electrode material 162, may be 50 nm and less. An insulation layer 161 physically and electrically separates the gate electrode material 162 from the channel region of the transistor 150.
The gate structure 160 may have been formed according to an HKMG approach. HKMG technology is usually preferred for gate lengths of about 50 nm or smaller. In this case, the insulation layer 161 may be one of the high-k gate dielectric materials well known in the art. For example, a non-exhaustive list of high-k materials which may be used in transistor gates has been given above.
The gate electrode structure 160 may also comprise a gate metal layer 162a, for instance in the form of tantalum nitride and the like, possibly in combination with a work function metal species, such as aluminum and the like. The gate metal layer 162a is typically formed above the insulation layer 161, thereby adjusting an appropriate work function and thus threshold voltage of the transistor 150. Furthermore, the gate electrode structure may be laterally delimited by a spacer structure 163 which may comprise one or more dielectric materials such as, for example, silicon nitride, silicon dioxide, silicon oxynitride and the like. For example, the spacer structure 163 may comprise appropriate protective liner materials for laterally encapsulating sensitive gate materials, such as the insulation layer 161 and, in particular, the metal layer 162a. 
The device fabrication flow may then continue in a conventional manner by performing the subsequent operations which might include: one or more than one ion implantations performed so as to define the source and drain regions of the FET, one or more silicidation steps, and deposition of one or more insulating layers onto the device surface.
As said above, the thickness of the channel semiconductor alloy layer is a crucial parameter affecting the threshold voltage of a FET and, especially, of a P-channel FET. For example, when SiGe alloy layers are used, the concentration of Ge in the film typically depends on the film thickness. In general, the different thicknesses of the semiconductor layer may critically affect the transistor threshold voltage due to the variation of band structure and of band-gap with respect to the film thickness.
In order for the threshold voltage to assume one and the same value for all transistors included in the semiconductor device, it is necessary that the thickness of the channel semiconductor alloy layer is uniform across the whole device surface.
Two main factors affect the uniformity of the channel semiconductor alloy layer, namely, the quality of the deposition process and the cleaning steps performed on the device surface after the layer deposition.
Fluctuations in the thickness of the channel semiconductor alloy layer straight after the deposition may be reduced to a minimum by using a highly conformal deposition technique. Several attempts have been made in this direction, achieving semiconductor alloy layers, e.g., SiGe alloy layers, with satisfactory thickness uniformity upon deposition.
However, the device surface, for example the wafer surface, typically undergoes one or more cleaning steps after the channel semiconductor alloy layer has been deposited. These cleaning steps may include wet or dry etches, as said above. The semiconductor alloy layer turns out to be particularly sensitive to the etching caused by the cleaning. Thus, as a result of surface cleaning, a pronounced thickness fluctuation is observed across the channel semiconductor alloy layer.
One more problem is the variation of thickness of the semiconductor alloy layer depending on the particular area of the device surface. Even if one well-established and highly conformal growing method is used, the channel semiconductor alloy layer turns out to have different thicknesses in different device areas. This thickness variation depends mainly on the fact that active regions formed in different device areas generally extend by different widths, thus having different surface areas. For instance, due to the small island size, transistors formed in a device area corresponding to a static random access memory (SRAM) area typically have a channel semiconductor alloy layer about 3 nm thicker than a transistor formed in an area occupied by a central processing unit (CPU).
This effect, also known as “pull-up issue” or “mushroom head,” is due to the inter-action between the deposited semiconductor alloy, e.g., SiGe, with the edges of the separation regions delimiting the active regions. Let us suppose that the surface of the substrate onto which the semiconductor alloy layer is deposited lies on a horizontal plane. Usually, the portion of the semiconductor alloy layer lying in proximity to the boundary between an active region and an isolation region forms a bump resulting in a portion of the layer with a larger thickness than the average layer thickness. The portion with an increased thickness extends across the horizontal plane towards the center of the active region by a certain length. If the active region extends across the horizontal plane by a length or a width that are comparable to or less than the length of the layer portion including the bump, then bumps originated from different points along the boundary of the active regions may interact with each other. In particular, bumps formed from different points of the active region boundary might overlap, thus resulting in a bulge of the semiconductor alloy layer at a central position across the surface of the active area.
The thickness variation of the semiconductor alloy layer cannot be compensated for by depositing a semiconductor layer with different thicknesses depending on the area across the surface. Since channel semiconductor alloy layers are processed at the wafer level, it is generally not possible to adjust the thickness of the semiconductor alloy layer depending on the particular device area onto which it is formed. Conversely, a channel semiconductor alloy layer, for example a channel SiGe layer, has to be grown in the course of a single deposition process, wherein the thickness cannot be locally controlled with respect to the position on the wafer. This means that, unless a deposition mask is used, a channel semiconductor alloy layer can only be formed by uniformly depositing the same amount of material across the entire wafer surface. This results in a variable thickness of the deposited layer depending on the local geometry of the device.
Therefore, a method is desirable which allows one to grow channel semiconductor alloy layers with a uniform thickness not changing upon device cleaning. It is also desirable to have the option of locally adjusting the thickness of the channel semiconductor alloy layer depending on the particular device area, even when the channel semiconductor alloy layer is deposited by means of a single-step process.